Interrupt Module

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Three interrupt signals are available for use at the system level, one from each timer counter. An interrupt occurs when a bit in the interrupt enable register and the corresponding bit in the interrupt detect register are both set. The resulting ANDed outputs are then ORed to generate the system interrupt signal. The interrupt register takes the interrupt signals from the timer-counter module and stores them until the register is read. When the interrupt register is read by the processor, it is reset. To enable an interrupt, it is necessary to write a 1 to the corresponding bit position in the interrupt enable register.