Interrupt Register Channels

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Each interrupt channel has six registers. Two registers are for sending an interrupt and four registers are for receiving an interrupt. The trigger and observation registers are used to send and monitor interrupts. The status/clear, mask, disable, and enable registers are used to receive an interrupt.

There are eleven sets of interrupt registers for use by any processor, except IPI channels {3:6}, which are hardwired for the PMU. The default and hardwired channel assignments are shown in This Figure. Default channel assignments are defined in the Xilinx software and supported by the master IDs configured in the XPPU after reset.

Figure 13-5:      IPI Interrupt Channel Architecture

X-Ref Target - Figure 13-5

X19837-interrupt-channel-architecture.jpg

The non-PMU IRQ system interrupts are bused to four places, as follows.

Note:   It is the responsibility of the individual masters to mask any unwanted IPIs in their own GIC.

RPU GIC uses the GICv1.0 architecture and is controlled by the RPU.

APU GIC uses the GICv2.0 architecture and is controlled by the APU.

GIC proxy is a Xilinx architecture for the PMU external interrupt controller and is controlled by the PMU.

PL outputs include four signals from the PS to the PL.

The PMU IRQ signals are only routed to the PMU.