Interrupt Register Descriptions

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Each processor is assigned to a set of six IPI registers divided into sending and receiving interrupts. The IPI interrupt register functionality is provided in Table: IPI Interrupt Register Functionality.

Table 13-2:      IPI Interrupt Register Functionality

Channel Activity

Register Name

Acronym

Bit Writes

Bit Reads

Write a 1

Write a 0

Read a 1

Read a 0

Send interrupt

Trigger

TRIG

Assert interrupt

Ignored

Write only

Observation

OBS

Read only

Interrupt request asserted.

Interrupt request not asserted.

Receive interrupt

Status and clear

ISR

Clear bit

Ignored

Interrupt request asserted.

Interrupt request not asserted.

Mask

IMR

Read only

IRQ not generated if status bit is asserted.

IRQ generated if status bit is asserted.

Mask enable

IER

Set IMR = 1

Ignored

Write only

Mask disable

IDR

Set IMR = 0

Ignored

Write only