Interrupt Sources

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Several events in the DDR memory controller can assert IRQ 144. The interrupts from the following sources are managed by the DDR_QOS_CTRL.QOS_IRQ_{STATUS, MASK} registers.

Correctable ECC error [DDR_ECC_CORERR].

Uncorrectable ECC error.

DFI initialization complete [DFI_INIT_COMP].

DFI parity error due to mode register set (MRS) [DFI_ALT_ERR_FTL].

DFI parity error counter reaches to its maximum count [DFI_ALT_ERR_MAX].

DFI parity or CRC error detected on the DFI interface [DFI_ALT_ERR].

Performance counter interrupt when register copy is done [PC_COPY_DONE].

Invalid DDR memory controller register access [INV_APB].

All interrupts from the list, except for DFI initialization complete, must be cleared in both the QoS controller and DDR controller by writing to their respective clear registers. The steps that are required for clearing interrupts are listed.

1.Clear the interrupt in the DDR controller by writing to the respective clear register.

2.Clear the interrupt in the QoS controller by writing to the DDR_QOS_CTRL.qos_irq_status register.