Interrupt Status Register

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The bits in the GIC proxy status registers GICP{0:4}_IRQ_STATUS are sticky and remain asserted after the source of the interrupt has deasserted its signal. The minimum interrupt pulse width for detection is four clock periods of the GIC proxy unit, which is normally a 100 MHz clock resulting in a minimum 40 ns pulse width. A shorter pulse width might also be detected. The status register bits are cleared by writing a 1 to them. The status register shows the interrupt state before the mask is applied. This register can be polled to determine if the event occurred or did not occur, irrespective of the state of the associated mask bit. Software acknowledges the interrupt by clearing this register.