Interrupt and Status Registers

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

There are two status registers that can be read by software. Both show raw status. The Chnl_int_sts register can be read for status and generate an interrupt. The Channel_sts register can only be read for status.

The Chnl_int_sts register is sticky; once a bit is set, the bit stays set until software clears it. Write a 1 to clear a bit. This register is bit-wise AND'ed with the Intrpt_mask mask register. If any of the bit-wise AND functions have a result = 1, then the UART interrupt is asserted to the PS interrupt controller.

Channel_sts: Read-only raw status. Writes are ignored.

The various FIFO and system indicators are routed to the uart.Channel_sts register and/or the uart.Chnl_int_sts register as shown in This Figure.

Figure 21-7:      Interrupts and Status Signals

X-Ref Target - Figure 21-7

X19861-interrupts-status-signals.jpg

The interrupt registers and bit fields are summarized in Table: UART Interrupt Status Bits.

Table 21-2:      UART Interrupt Status Bits

Interrupt Register Names and Bit Assignments

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

uart.Intrpt_en

uart.Intrpt_dis

uart.Intrpt_mask

uart.Chnl_int_sts

x

RBRK

TOVR

TNFUL

TTRIG

DMS

TOUT

PARITY

FRAMING

OVER

TXFUL

TXEMPTY

RXFULL

RXEMPTY

RXOVR

uart.Channel_sts

TNFUL

TTRIG

FLOWDEL

TACTIVE

RACTIVE

X

X

X

X

X

TXFUL

TXEMPTY

RXFULL

RXEMPTY

RXOVR