Interrupt to RPU and APU GIC Interrupt Controllers

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The pulse length of four clock cycles (SWDT.MODE[IRQLN] = 2'b00) from the watchdog timer is sufficient for the interrupt controller to capture the interrupt using rising-edge sensitivity.