Interrupts to PMU

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The state of the GIC proxy interrupts after the interrupt mask are OR'ed together on a per register basis to set bits in the LPD_SLCR.GICP_PMU_IRQ_STATUS register. For example, if any unmasked interrupt in the LPD_GIC_PROXY.GICP0_IRQ_STATUS register is active, then the LPD_SLCR.GICP_PMU_IRQ_STATUS [src0] bit is set by the interrupt hardware.

The PMU can read the GICP_PMU_IRQ_{STATUS, MASK} registers to determine which GIC proxy register allowed the interrupt to propagate. Finally, the GIC proxy status and mask registers that were determined to propagate the interrupt can be read to determine which system element caused the interrupt.