Introduction to the UltraScale Architecture

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

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2.4 English

The AMD UltraScale™ architecture enables multi-hundred gigabit-per-second levels of system performance with smart processing, while efficiently routing and processing data on-chip. UltraScale architecture-based devices address a vast spectrum of high-bandwidth, high-utilization system requirements by using industry-leading technical innovations, including next-generation routing, ASIC-like clocking, 3D-on-3D ICs, multiprocessor SoC technologies, and new power reduction features. The devices share many building blocks, providing scalability across process nodes and product families to leverage system-level investment across platforms.

All AMD ZynqUltraScale+ devices provide 64-bit processor scalability while combining real-time control hard engines for graphics, video, waveform, and packet processing capabilities in the programmable logic. Integrating an Arm®-based system for advanced analytics and on-chip programmable logic for task acceleration creates unlimited possibilities for applications including 5G Wireless, next generation ADAS, and Industrial Internet-of-Things.

The RFSoC devices are similar to the basic MPSoC devices with the addition of key RF subsystems for multi-band, multi-mode cellular radios and cable infrastructure (DOCSIS). The RFSoC devices combine the processing system with programmable logic located near RF-ADCs, RF-DACs, and soft-decision FEC (SD-FEC) units to enable a complete software-defined radio including direct RF sampling data converters, enabling CPRI™ and multi-gigabit Ethernet-to-RF on a single, highly programmable SoC.

Table: Functional Units and Peripherals shows the main functional units and peripherals. For more information on the TRM, see References, AMD Documentation Navigator, and the Zynq UltraScale+ Documentation website [Ref 1].