Isolation is generally used to isolate signals from a powered-up domain and a powered-down domain to prevent crowbar currents affecting the proper functioning of the blocks. Isolation ensures that the outputs of the domains are clamped to a known value. The PMU facilitates isolation of various power domains. This can be done by setting appropriate bits in the REQ_ISO_TRIG global register. For the PMU_GLOBAL.REQ_ISO_STATUS register description, see the Zynq UltraScale+ MPSoC Register Reference (UG1087) [Ref 4]. Three bits control domain isolation between the low-power, full-power, and PL domain. Different combinations of isolation are available. By writing to bit 0 of the REQ_ISO_TRIG register and the REQ_ISO_INT_MASK register, the full-power domain can be isolated from the low-power domain and the PL domain. By writing to bit 1 of these registers, the PS is isolated from the PL. By writing to bit 2 the PS and the PL are isolated, with the exception of the PCAP interface. Finally, to lock isolation on the full-power domain, write to bit 4.