JTAG Chain Boot States

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The JTAG chain is configured by the CSU BootROM during boot based on the security state of the boot. The values for the JTAG chain configuration registers for each boot mode are shown in Table: POR Boot State and Secure Boot Mode to Table: Non-secure Boot Mode. The state immediately after a POR is a secure state, but the state changes for non-secure device and PJTAG boot modes.

Table 39-1:      POR Boot State and Secure Boot Mode

Register

Value

Description

JTAG_CHAIN_STATUS

0x0

Arm DAP and PL TAP are disabled.

JTAG_DAP_CFG

0x0

DAP debug disabled.

JTAG_SEC

0x0

Security gates enabled.

Table 39-2:      PJTAG Boot Mode

Register

Value

Description

JTAG_CHAIN_STATUS (ro)

0x1

Arm DAP is disabled.
PL TAP is enabled.

JTAG_DAP_CFG (r/w)

0xFF

DAP debug enabled (invasive and non-invasive).

JTAG_SEC (r/w)

0x3F

Security gates disabled.

 

 

 

Table 39-3:      Non-secure Boot Mode

Register

Value

Description

JTAG_CHAIN_STATUS

0x3

Arm DAP and PL TAP are enabled.

JTAG_DAP_CFG

0x3F

DAP debug enabled (invasive and non-invasive).

JTAG_SEC

0x3F

Security gates disabled.