JTAG Chain Configuration

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The JTAG chain can be configured to have the PS TAP and the Arm DAP controllers, or all three controllers on a single daisy chain. In each case, the instruction length remains fixed at 16 bits. When a controller is not present, dummy bits are accepted.

The JTAG chain configuration is controlled by the JTAG_DAP_CFG register. This register can be written to by an AXI master accessing a CSU register, by the PS TAP controller using the JTAG_CTRL instruction, or by issuing the JTAG_CTRL instruction to the PS TAP and then writing in the new configuration.

JTAG_CTRL register bits 1 and 0:

00: PS TAP controller

01: PS and PL TAP controllers

10: PS TAP and Arm DAP controllers

11: All three controllers: PS TAP, PL TAP, and Arm DAP

 

IMPORTANT:   Any time the number of controllers on the JTAG chain is switched, the PS TAP, PL TAP, and Arm DAP controller state machines must be synchronized by holding the TMS High for five cycles of the TCK.