JTAG Functional Description

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

JTAG is the centerpiece of the debug features for software and PL development, and also serves as a test port for board-level test. Consequently, it is critical to keep JTAG as simple as possible with the least hardware dependency.

The JTAG architecture has three TAP controllers:

PS TAP (main PS controller with IDCODE).

PL TAP (PL configuration and boundary scan).

DAP (Arm debug of RPU and APU using CoreSight).

After a POR reset (PS_POR_B or internal POR), only the dedicated PS JTAG signal pins are activated and only the PS TAP controller is visible on the JTAG chain. The PS TAP controller has limited functionality until the configuration security unit (CSU) has completed the PS boot sequence and granted further functionality.

Full functionality of the PS TAP controller and access to the DAP and PL TAP controllers can be made available after the boot sequence using a special command sent to the PS TAP controller.