JTAG and DAP Overview

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The JTAG chain is accessed using a standard IEEE Std 1149.1 JTAG interface. It is designed to facilitate system debug software and PL development, and to serve as a test port for boundary scan for board-level testing. The JTAG interfaces and controllers are described in JTAG Chain:.

Single JTAG port in the PS to support both PS and PL.

Arm DAP for loading programs, system test, and PS debug.