JTAG and Debug Clocks

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Most of the components in the CoreSight debug logic have only one clock input. Power domain crossings use APB asynchronous bridges, and ATB asynchronous bridges. Table: Clocks lists the JTAG and debug clocks.

 

 

 

 

Table 39-10:      Clocks

Clock Name

Power Domain

Source

Where Used

JTAG test clock

Aux

TCK input pin

JTAG-DP

AHB_CLK

LPD

SysOsc (internal ring oscillator)

JTAG-DP, AXI-AP, APB-AP, and JTAG-AP

DBG_LPD_CLK

LPD

CRL_APB.DBG_LPD_CTRL

RPU debug logic and funnel

DBG_FPD_CLK0

FPD

CRF_APB.DBG_FPD_CTRL

APU debug logic

DBG_FPD_CLK1

FPD

STM, funnel, ETF, ETR, TPIU, CTIs, and CTMs

DBG_TSTMP_CLK

FPD

Timestamp network

DBG_TRACE_CLK

FPD

CRF_APB.DBG_TRACE_CTRL

TPIU, double data rate

PL_PS_TRACE_CLK

FPD

PL input

TPIU, double data rate