LBIST

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The LBIST covers more than 90% of the system units. The LBIST operations are run once during the hardware boot. If an LBIST operation fails, a single status flag is raised in the JTAG status register, and the system stalls. This failure can be detected by reading the JTAG status [11] bit field; however, it cannot be determined which system element failed the LBIST operation.

LBIST operations require approx. 250 mA supply (LPD+FPD). After the LBIST goes to the scan clear (zeroization) state, the supply current is released back to the normal system.

For increased safety against an SEU, the LBIST trigger signal from the hardware can be gated off during normal system operation using the PMU global register bit SAFETY_GATE [LBIST_Enable].

The primary goal for the LBIST is to detect latent faults at boot time. Using the LBIST, these blocks are checked for latent faults:

Lock-step checkers such as the Cortex-R5F processor, PMU, and configuration security unit (CSU)

ECC generation and checking:

°On-chip memory (OCM), CSU, and PMU RAM

°Tightly coupled memory (TCM) and cache memory controllers

Xilinx memory protection unit (XMPU)

Common clock monitoring

PS SYSMON interface

PMU logic

Error monitoring logic

Reset controller

Note:   LBIST coverage does not include the logic in the crypto engines.