LBIST Boot Sequence

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

1.The PS_POR_B reset signal must be asserted during the power-up sequence. Voltage must remain stable during boot and normal operation.

2.To use the FPD, the VCC_PSINTFP power must be valid and stable before deasserting PS_POR_B; otherwise, the LBIST disables the FPD during the boot process making it unavailable. The FPD remains disabled until the next POR with valid FPD power.

3.The PS_MGTRAVCC power must be valid and stable during the LBIST operation for the transceivers to be operational; otherwise they are disabled by the LBIST.

4.The LBIST controllers are in the LPD and operate before the FPD is enabled.

5.The PS_INIT_B signal is internally driven low during the LBIST operation and the signal must not be externally driven high; otherwise, the LBIST operation fails.

6.The PS_PROG_B signal must remain high during the LBIST operation and must not be externally driven low; otherwise, the LBIST operation fails.

7.The LBIST is activated when PS_POR_B is deasserted. Asserting PS_POR_B stops the LBIST operations.

 

IMPORTANT:   Care must be taken when initiating LBIST operations. The system element must be powered-up, clocked, and held in reset. When the LBIST operation is completed, the logic is left in its POR state.

The LBIST failure state recovers only after the power cycle or PS_POR_B is asserted. If the LBIST error is not recoverable, there is no masking of the error or the LBIST eFUSE option once it is enabled.