LPD-PL Interfaces

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The high-performance interface port (S_AXI_LPD) from the PL to the LPD includes the following features.

Configurable to 32, 64, or 128-bit data widths on the PL side.

Preferred interface for PL access to the OCM and TCMs with the lowest latency.

Access to all of the global address map (especially to access the PS DDR memory).

This port can be used in physical or virtual mode by setting the AxUSER bit. In virtual mode, it cannot directly access the LPD. Instead, virtual mode accesses are routed as follows. AxUSER should be set to 1'b1 to select virtual mode or 1'b0 to select physical mode.

PL ®  LPD ®  FPD (SMMU/CCI) ®  LPD

The S_AXI_LPD is a PL interface that connects into the low-power domain. For situations where the FP domain is powered down, this interface provides a high-performance mastering capability from the PL. Due to the interconnect topology, this port has a relatively long latency to DDR.

The low-latency interface port (M_AXI_HPM0_LPD) from the LPD to the PL includes the following features.

Configurable to 32, 64, or 128-bit data widths on the PL side.

AXI4 access in the PL, but is limited to a burst length of 16.

Responds to lowest 512 MB memory in LPD's 32-bit address space.

Enables direct access to the PL (for example for block RAM, DDR) for the safety use cases.

LPD bus masters can use the M_AXI_HPM0_LPD interface to access the PL without the FPD being powered-up.

 

IMPORTANT:   Exclusive access by the APU cannot be made to the M_AXI_HPM0_LPD signal due to an ID converter in the path.