Legacy Linear Addressing

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The legacy Quad-SPI has 128 MB of allocated system memory and requires a 27-bit address [26 down to 0] to decode the address space. Register bit 27 of a linear Quad-SPI configuration register is added to enable the 4-byte address capability. When enabled, a 32-bit address is formed by concatenating the lower 27 bits received on the AXI address bus with five zeros.

When two flash devices are cascaded and the 4-byte address feature enabled, then bit 26 is used to select the flash. Setting bit 26 of the AXI address bus selects the upper flash by using the lower 26 bits of the AXI address bus and appending the MSB 6 bits with zeros to form a 4-byte address to the flash. Setting bit 26 to zero selects the lower flash by using the lower 26 bits of the AXI address bus and appending the MSB 6 bits with zeros to form a 4-byte address to the flash.

When two flash devices are cascaded and the 4-byte address feature is not enabled, then bit 26 is used to select the flash. Setting bit 26 of the AXI address bus selects the upper flash and the lower 24 bits of the AXI address bus are used to address the flash. To select the lower flash, bit 26 is set to zero and the lower 24 bits of the AXI address bus are used to address the flash.

When two flash devices are connected in parallel and the 4-byte address feature is enabled, then to access the flash pad bit 26 down to bit 1 with seven zeros. Bit 0 is discarded because the memory content is shared across the memories.

When two flash devices are connected in parallel and the 4-byte address feature is disabled, then to access the flash use bit 24 down to bit 1. Bit 0 is discarded because the memory content is shared across the memories.

When a single flash is connected and the 4-byte address feature is enabled, then to access the flash pad bit 25 down to bit 0 of the AXI address bus with six zeros.

When a single flash is connected and the 4-byte address feature is disabled, then to access the flash use bits 23 down to bit 0 of the AXI address.