Legacy Quad-SPI AXI Read Command Processing

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

AXI read-burst commands are translated into SPI flash read instructions that are sent to the Quad-SPI controller TXFIFO. The controller transmit logic retrieves the read instruction from the TXFIFO and passes them to the SPI flash memory device according to the SPI protocol.

A 64-deep FIFO is used to provide read data buffering to hold up to four burst of 16 data. Since the RXFIFO starts receiving data as soon as the chip-select signal is active, the linear address module removes any incoming data that corresponds to the instruction code, the address, and the dummy cycles, and responses to the AXI read instruction with valid data.