To reduce the I/O pin count, the controller also supports up to two SPI flash memories in a shared bus configuration, as shown in This Figure. This configuration increase the maximum addressable SPI flash memory from 256 MB (28-bit address) to 512 MB (29-bit address), but the throughput remains the same as in single memory mode. In this 4-bit stacked I/O configuration, the device level XIP mode (read instruction codes of BBh and EBh) is not supported.
The lower SPI flash memory should always be connected when using the linear Quad-SPI memory subsystem. The upper flash memory is optional. The total address space is 512 MB with a 29-bit address. In linear address mode, the AXI address bit 28 determines the upper or lower memory page. All of the commands are executed by the device selected by address bit 28.