Legacy Quad-SPI Dual Slave Select 8-bit Parallel I/O

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The controller supports up to two SPI flash memories operating in parallel, as shown in This Figure. This configuration increase the maximum addressable SPI flash memory from 16 MB (24-bit address) to 32 MB (25-bit address). In this configuration, the device level XIP mode is not supported.

Figure 24-6:      Legacy Quad-SPI Dual Slave Select 8-bit Parallel I/O

X-Ref Target - Figure 24-6

X17789-dual-ss-8-bit-block.jpg

For 8-bit parallel configuration, the even bits of the data words are located in the lower memory and the odd bits of data are located in the upper memory. The Quad-SPI controller manages the data in linear mode. The controller reads from the two Quad-SPI devices and ORs (OR operation) the status information from both devices before writing the status data in the RXFIFO. This Figure shows the data bit arrangement of a 32-bit data word for an 8-bit parallel configuration. Table 12-8 shows the Quad-SPI commands in dual Quad-SPI parallel mode.

Table 24-9:      Quad‐SPI Dual Slave Select 8‐bit Parallel I/O Data Management

Single Device

7

6

5

4

3

2

1

0

15

14

13

12

11

10

9

8

23

22

21

20

19

18

17

16

31

30

29

28

27

26

25

24

byte 0

byte 1

byte 2

byte 3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Dual Devices

Lower Memory

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

4

2

0

14

12

10

8

22

20

18

16

30

28

26

24

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Dual Devices

Upper Memory

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

5

3

1

15

13

11

9

23

21

19

17

31

29

27

25

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

byte 0

byte 1

byte 2

byte 3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 24-10:      Quad-SPI Command List for Dual Quad-SPI Parallel Mode

Command

Dual Parallel Quad-SPI Controller

Sector Erase

The Quad-SPI controller sends and erase command to both devices. A 64 KB erase operation erases each device, which effectively erases a combined 128 KB from both memories.

Read ID

The received data is taken from the lower flash bus and places it in RXD. There is no need to combine data. The upper and lower flash devices must be identical when using the parallel flash mode.

Read

The even and odd data bits are read from both devices and are interleaved as shown in Table: Quad‐SPI Dual Slave Select 8‐bit Parallel I/O Data Management.

RDSR

The work-in-progress (WIP) bit from both devices are OR'ed together to form the LSB of the data read. The other seven bits come from the lower bus.

In 8-bit parallel configuration, the total addressable memory size is 512 MB.This requires a 29-bit address. All accesses to memory must be word aligned and have double-byte resolution. In linear mode, the Quad-SPI controller divides the AXI address by two and sends the divided address to the Quad-SPI device.

Note:   In a dual parallel configuration of two flash devices, when GQSPI is used to write to flash, and LQSPI in linear mode is used to read data from flash, the data read does not match with the data write. This data mismatch is caused by the difference in the handling of data by the two controllers in dual parallel configuration. GQSPI writes are "byte striped" and LQSPI reads are "bit interleaved". The application software should handle this interoperability between LQSPI and GQSPI in a dual parallel configuration.