Legacy Quad-SPI I/O Interface

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The I/O signals are available through the MIO pins. The Quad-SPI controller supports up to two SPI flash memories in either a shared or separate bus configuration. The controller supports operation in the following configurations.

Quad-SPI single slave select 4-bit I/O.

Quad-SPI dual slave select 8-bit parallel I/O.

Quad-SPI dual slave select 4-bit stacked I/O.

 

IMPORTANT:   QSPI0 should always be present when using the Quad-SPI memory subsystem. QSPI1 is optional and is only required for a two-memory arrangement. Therefore, QSPI1 cannot be used alone.