Legacy Quad-SPI Linear Address Mode

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The controller has a 32-bit AXI slave interface to support linear address mapping for read operations. When a master issues an AXI read command through this port, the Quad-SPI controller generates commands to load the corresponding memory data and send it back through the AXI interface.

In linear address mode, the flash memory subsystem is similar to a typical read-only memory with an AXI interface that supports a command pipeline depth of four. By reducing the amount of software overhead, the linear address mode improves the overall throughput of the read memory. From a software perspective, there is no perceived difference between accessing the legacy Quad-SPI memory subsystem and that of other ROMs, except for the potentially longer latency.

A transfer to linear address mode occurs when the qspi.LQSPl_CFG [LQ_MODE] bit is set to 1. Before entering into linear address mode, both the TXFIFO and RXFIFO must be empty. Once the qspi.LQSPI_CFG [LQ_MODE] bit is set, the FIFOs automatically control the legacy Quad-SPI module and I/O access to TXD and RXD are undefined.

In linear address mode, the CS pins are automatically controlled by the QSPI controller. Before a transition into legacy Quad-SPI linear address mode, both of the qspi.Config [Man_start_en] and qspi.Config[PCS] must be zero.

A simplified block diagram of the controller showing the linear and I/O portions is shown in This Figure.