Level2 AXI Interfaces

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

There are three distinct advanced eXtensible interfaces (AXI) to the rest of the MPSoC. The first is the AXI master interface. There is also a separate AXI peripheral interface that connects to the GIC and an AXI slave port provided to allow external masters to access ICACHE, DCACHE, and TCM RAMs. Access from the AXI slave port to the caches is only provided for use during debug. The L2 AXI interfaces enable the L1 memory system to have access to peripherals and to external memory using an AXI master and AXI slave port and the peripheral ports.