Linear Address Mode AXI Interface Operation

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Only AXI read commands are supported by the linear address mode. All valid write addresses and write data are acknowledged immediately but are ignored, that is, no corresponding programming (write) of the flash memory is carried out. All AXI writes generate an external AXI slave error (SLVERR) on the write response channel.

Both increment or wrapping address burst reads are supported. Fixed address bursts are not supported and cause an SLVERR response. Therefore, the only recognized ARBURST[1:0] value is either 2'b01 or 2'b10. All read accesses must be word-aligned and the data width must be 32 bits (no narrow burst transfers are allowed).

Table: Ignored AXI Read Address Channel Signals lists the read address channel signals from a master that are ignored by the interface.

Table 24-5:      Ignored AXI Read Address Channel Signals

Signal

Value

ARADDR[1:0]

Ignored, assumed to be 0 (always assumed to be word aligned).

ARSIZE[2:0]

Ignored, always a 32-bit interface.

ARLOCK[1:0]

Ignored

ARCACHE[3:0]

Ignored

ARPROT[2:0]

Ignored

The AXI slave interface provides a read acceptance capability of four to accept up to four outstanding AXI read commands.