Long Acquisition Time

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

In auto-sequencer mode, the SYSMON unit waits four ADC clock cycles before sampling the analog input. In the PL SYSMON, the settling time can be extended to ten clock cycles for the external voltage measurements by setting bits in the SEQ_ACQ registers on a per channel basis. The long acquisition time extends the settling time after being selected by the analog multiplexer. The long acquisition time feature applies to the VP_VN, VUSER{0:3}, and VAUX{P, N}{0:15} channels of the PL SYSMON. The PS SYSMON does not use the long acquisition time feature.