Loopback Mode

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Loopback is implemented in the secure-stream switch hardware. It is not internal to the CSU DMA. The CSUDMA.CSUDMA_DST_CTRL [SSS_FIFOTHRESH] bit field controls the level of the DST FIFO to result in asserting the data_out_fifo_level_hit signal on the DST interface. This can be used to flow control data between the SRC and DST FIFOs in loopback mode. If loopback mode is used, where SRC data is looped around in the secure-stream switch and presented to the DST channel, the software should always start the DST channel before starting the SRC channel. This ensures that the DST channel is always ready once the first piece of data present at its secure-stream switch interface. Refer to the Programming the CSU DMA section for details on the CSU DMA programming sequence.