Low Latency (High Priority) Masters

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

For some masters, read latency is key to meeting performance requirements. In the PS, the three key low-latency masters are the APU, RPU, and SMMU. Without low-latency access to memory, the CPU spends most of the time in idle waiting for data to either be fetched from or stored to external memory space.