Low Power Operation

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The OCM memory implements four different banks with the two MSBs of the address determining the bank that is accessed. Each bank is implemented in a separate power-gated island that is controlled by the PMU. The PMU can also configure the RAMs in a retention state, in addition to the complete powered-down state. In the case of an access to a bank that is powered down or is in retention, the OCM generates an address decode error.