MAC Filtering

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The MAC filter determines which frames should be written to the AXI interface FIFO and onto the DMA controller. Whether a frame is passed depends on what is enabled in the network configuration register, the state of the I/O matching signals, the contents of the specific address, type, and hash registers and the frame's destination address and type field.

If bit [25] of the network configuration register is not set, a frame is not copied to memory if the gigabit Ethernet controller is transmitting in half-duplex mode at the time a destination address is received.

Ethernet frames are transmitted a byte at a time, least significant bit first. The first six bytes (48 bits) of an Ethernet frame make up the destination address. The first bit of the destination address, which is the LSB of the first byte of the frame, is the group or individual bit. This is one for multicast addresses and zero for unicast. The all-ones address is the broadcast address and a special case of multicast.

The gigabit Ethernet controller supports recognition of four specific addresses. Each specific address requires two registers, specific address register bottom and specific address register top. Specific address register bottom stores the first four bytes of the destination address and specific address register top contains the last two bytes. The addresses stored can be specific, group, local, or universal.

The destination address of received frames is compared against the data stored in the specific address registers once activated. The addresses are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when the specific address register top is written. If a receive frame address matches an active address, the frame is written to the FIFO and on to the DMA controller, if used.

Frames can be filtered using the type ID field for matching. Four type ID registers exist in the register address space and each can be enabled for matching by writing a one to the MSBs (bit [31]) of the respective register. When a frame is received, the matching is implemented as an OR function of the various types of match.

The contents of each type ID registers (when enabled) are compared against the length/type ID of the frame being received (for example, bytes 13 and 14 in non-VLAN and non-SNAP encapsulated frames) and copied to memory if a match is found. The encoded type ID match bits (word 1, bit [22] and bit [23]) in the receive buffer descriptor status are set indicating which type ID register generated the match, if the receive checksum offload is disabled. The reset state of the type ID registers is zero, for this reason, each is initially disabled.

The following example illustrates the use of the address and type ID match registers for a MAC address of 21:43:65:87:A9:CB.

Preamble 55

SFD D5

DA (Octet 0 - LSB) 21

DA (Octet 1) 43

DA (Octet 2) 65

DA (Octet 3) 87

DA (Octet 4) A9

DA (Octet 5 - MSB) CB

SA (LSB) 00*

SA 00*

SA 00*

SA 00*

SA 00*

SA (MSB) 00*

Type ID (MSB) 43

Type ID (LSB) 21

Note: * - contains the address of the transmitting device.

The sequence shows the beginning of an Ethernet frame. Byte order of transmission is from top to bottom. For a successful match to specific address 1, the following address matching registers must be set up.

Specific address 1 bottom (address 0x088) 0x87654321.

Specific address 1 top (address 0x08C) 0x0000CBA9.

And for a successful match to the type ID, the following type ID match 1 register must be set up.

Type ID match 1 (address 0x0A8) 0x80004321.