The MAC transmitter can operate in either half-duplex or full-duplex mode, and transmits frames in accordance with the Ethernet IEEE Std 802.3. In half-duplex mode, the CSMA/CD protocol of the IEEE Std 802.3 specification is followed.
Frame assembly starts by adding the preamble and the start frame delimiter. Data is taken from the transmit FIFO a word at a time. When the controller is configured for gigabit operation, the data output to the PHY uses all eight bits of the txd[7:0] output. In 10/100 mode, transmit data to the PHY is nibble wide and the least significant nibble is first using txd[3:0] with txd[7:4] tied to logic 0.
If necessary, padding is added to take the frame length to 60 bytes. CRC is calculated using an order 32-bit polynomial. This is inverted and appended to the end of the frame taking the frame length to a minimum of 64 bytes. If the no-CRC bit is set in the second word of the last buffer descriptor of a transmit frame, neither pad nor CRC are appended. The no-CRC bit can also be set through the FIFO.
In full-duplex mode (at all data rates), frames are transmitted immediately. Back-to-back frames are transmitted at least 96-bit times apart to check the interframe gap.
In half-duplex mode, the transmitter checks carrier sense. If asserted, the transmitter waits for the signal to become inactive, and then starts transmission after the interframe gap of 96-bit times. If the collision signal is asserted during transmission, the transmitter transmits a jam sequence of 32 bits taken from the data register and then retries transmission after the backoff time has elapsed. If the collision occurs during either the preamble or SFD, then these fields are completed prior to generation of the jam sequence.
The backoff time is based on an XOR of the 10 least significant bits of the data coming from the transmit FIFO and a 10-bit pseudo-random number generator. The number of bits used depends on the number of collisions seen. After the first collision 1 bit is used, then the second 2 bits, and up to the maximum of 10 bits. All 10 bits are used above ten collisions. An error is indicated and no further attempts are made if 16 consecutive attempts cause a collision. This operation is compatible with the description in clause 126.96.36.199.5 of the IEEE Std 802.3 which refers to the truncated binary exponential backoff algorithm.
In 10/100 mode, both collisions and late collisions are treated identically, and backoff and retry are performed up to 16 times. When operating in gigabit mode, late collisions are treated as an exception and transmission is aborted, without retry. This condition is reported in the transmit buffer descriptor word  (late collision, bit ) and also in the transmit status register (late collision, bit ).
An interrupt can also be generated (if enabled) when this exception occurs, and bit  in the interrupt status register is set.
When bit  is set in the network configuration register the IPG can be stretched beyond 96 bits depending on the length of the previously transmitted frame and the value written to the stretch_ratio register. The least significant 8 bits of the stretch_ratio register multiply the previous frame length (including preamble) and the next significant 8 bits (+1 so as not to get a divide by zero) divide the frame length to generate the IPG. IPG stretch only works in full-duplex mode and when bit  is set in the network configuration register. The stretch_ratio register cannot be used to shrink the IPG below 96 bits.