MBIST Functionality

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

ROM code execution initiates MBIST clear on the entire LP domain minus the PMU or on the entire FP domain. When a memory is tested or cleared using the MBIST, the rest of the system can be functioning. For most of the blocks, RAM is accessed by the MBIST and it keeps the block RAM in the reset state when the RAM is accessed by the MBIST engine. For a few blocks, such as APU core processors, RAM is accessed by the MBIST through the core functional paths that can be interfered if the block is in reset. In such cases, Arm requires a small subset of inputs to the core to be tied off to specific values during the MBIST execution.

Setting a particular bit in the MBIST_RST, MBIST_PG_EN, and MBIST_SETUP registers starts the MBIST process on that particular block. The MBIST_DONE bit is set to indicate that the process is finished. MBIST_GOOD provides the status of the process by setting either 0 (fail) or 1 (success).

There are five control and status registers:

MBIST_RST rw

MBIST_PG_EN rw

MBIST_SETPU rw

MBIST_DONE ro

MBIST_GOOD ro

For the RAMs in:

APU, RPU cores

CANx, GEMx, USBx,

GPU, PCIe, SIOU

PS-PL AXI Interface RAMs

The MBIST units are listed by bit field in the Zynq UltraScale+ MPSoC Register Reference (UG1087) [Ref 4].