The MIO device pins are fundamental to the I/O connections for the LPD IOP controllers. Software routes the controllers I/O signals to the MIO pins using IOU_SLCR registers. When there are not enough MIO pins for the peripheral I/O, then the EMIO can be used to connect signals to PL I/O device pins and logic within the PL. Table: MIO-EMIO Signals and Interfaces lists the MIO-EMIO signals and interfaces.
RECOMMENDED: The routing of the IOP interface I/O signals must be configured as a group. That is, the signals within an interface must not be split and routed to different MIO pin groups. For example, if the SPI 0 CLK is routed to MIO pin 40, then the other signals of the SPI 0 interface must be routed to MIO pins 41 to 45. Similarly, the signals within an IOP interface must not be split between MIO and EMIO. However, unused signals within an IOP interface do not necessarily need to be routed. Each unused MIO pin can be configured as a GPIO.