MIO-EMIO Signals and Interfaces

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The MIO device pins are fundamental to the I/O connections for the LPD IOP controllers. Software routes the controllers I/O signals to the MIO pins using IOU_SLCR registers. When there are not enough MIO pins for the peripheral I/O, then the EMIO can be used to connect signals to PL I/O device pins and logic within the PL. Table: MIO-EMIO Signals and Interfaces lists the MIO-EMIO signals and interfaces.

 

RECOMMENDED:   The routing of the IOP interface I/O signals must be configured as a group. That is, the signals within an interface must not be split and routed to different MIO pin groups. For example, if the SPI 0 CLK is routed to MIO pin 40, then the other signals of the SPI 0 interface must be routed to MIO pins 41 to 45. Similarly, the signals within an IOP interface must not be split between MIO and EMIO. However, unused signals within an IOP interface do not necessarily need to be routed. Each unused MIO pin can be configured as a GPIO.

Table 2-7:      MIO-EMIO Signals and Interfaces

Interface

MIO Access

EMIO Access

Notes

GEM{0:3}

RGMII

GMII

MIO: 4-bit RGMII v2.0, external PHY, 250 MHz data rate.
EMIO: 8-bit GMII, RGMII v2.0 (HSTL), RGMII v1.3, MII, SGMII, 1000BASE-SX, and 1000BASE-LX in PL, 125 MHz data rate.

SDIO{0, 1}

Yes

Yes

The SDIO interface performance is reduced when using the EMIO interface.

USB{0, 1}

USB 2.0 to external ULPI PHY.

No

The USB 3.0 interface is routed to a GTR channel

I2C{0, 1}

Yes

Yes

 

SPI{0, 1}

Yes

Yes

The SPI interface performance is reduced when using the EMIO interface.

UART{0, 1}

Yes (RX, TX)

Yes (RX, TX, modem signals).

 

CAN{0, 1}

Yes

Yes

External PHY.

GPIO Banks {0:2}

Yes (up to 78)

No

 

GPIO Banks {3:5}

No

Yes (up to 96)

Input, output, and 3-state control.

Quad-SPI

Yes

No

 

NAND

Yes

No

 

LPD_SWDT,
FPD_SWDT

Yes

Yes

Reset and output pulse.

CSU_SWDT

No

No

 

TPIU Trace

Up to 16 bits

Up to 32 bits