Banks 0 to 2 of the GPIO peripheral are routed to device pins through the MIO. All MIO pin configuration registers in Table: MIO Control Registers use the IOU_SLCR register set.
Banks 0 to 2 of the GPIO peripheral are routed to device pins through the MIO. All MIO pin configuration registers in Table: MIO Control Registers use the IOU_SLCR register set.