MIO Pin Configuration

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Banks 0 to 2 of the GPIO peripheral are routed to device pins through the MIO. All MIO pin configuration registers in Table: MIO Control Registers use the IOU_SLCR register set.