The processing system (PS) contains three banks of 26-bit general-purpose multiplexed I/O (MIO) used by different peripherals. All the three banks can support LVCMOS18, LVCMOS25, and LVCMOS33 standards. The I/O that is used in conjunction with the PMU includes the UTMI+ low pin interface (ULPI) for one USB, six GPIs for wake and signaling, and six GPOs for power supply control and signaling. The I/O pins for power management and wake up are accessible from the GPO1 and GPI1 registers, respectively.
Among the six GPOs, the PMU ROM code uses GPO1 on MIO to control the FPD's VCC_PSINTFP power supply and GPO1 on MIO to control the PL's VCCINT power supply. Both pins are active high (1 is power on and 0 is power off). The other four GPO[2:5] signals can drive outputs onto the MIO[34:37] pins.
The Xilinx development boards assign functionality for the GPO[2:5] signals, but they can be re-assigned and controlled by PMU user firmware because they are not used by the PMU ROM code. The GPO signals and MIO pins are listed in Table: PMU General Purpose MIO Pins.