MIO Pins

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The PS uses the MIOs as described in Multiplexed I/O. The MIO pins are configured by accessing registers located in the IOU_SLCR register set. The default routing for the peripheral I/O signals is through the EMIO interface to the PL fabric. The pin availability for the I/O controller is often different between routing to the MIO pins versus the EMIO interface to the PL.

Table 2-4:      MIO Pins

Pin Name

Type

Direction

Description

PS_MIO[0:77]

Configurable pins, see Table: MIO Interfaces

Input/Output

Multiplexed I/Os are configured for the IOP controllers and other interfaces: SPI, QSPI, NAND, USB 2.0 ULPI, GEM Ethernet RGMII, SDIO, UART, GPIO, MDIO, SWDT, TTC, TPIU, PJTAG.