MIO and EMIO

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The PS and PL can be coupled with multiple interfaces and other signals to effectively integrate user-created hardware accelerators and other functions in the PL logic that are accessible to the processors. They can also access memory resources in the processing system. The PS I/O peripherals, including the static/flash memory interfaces share a multiplexed I/O (MIO) of up to 78 MIO pins. The peripherals can also use the I/Os in the PL domain for many controllers. This is done using the extended multiplexed I/O interface (EMIO).

The I/O peripheral signal availability on MIO and EMIO is summarized in Table: MIO-EMIO Signals and Interfaces. The MIO pin multiplexing functionality is described in Multiplexed I/O.