MODE Field

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The DPDMA supports two modes of operation (controlled by the mode bit (27) in the descriptor).

The contiguous mode is supported for systems where a large set of contiguous memory is available. The transfer size must be an integer multiple of the frame or line (the descriptor payload must end at a line or frame boundary). Software can choose to have a whole frame descriptor payload. The DPDMA uses the stride information along with the horizontal line resolution to determine the end of line and start of the next line.

For a pixel resolution of 4-bytes, it can take up to 20 KB to store a single line in memory. It is difficult to assign 20 KB of contiguous memory in the Linux environment. This creates a support requirement for the fragmented descriptor mode.

°A contiguous descriptor cannot store more than a single frames worth of data.

°The transfer size should be an integer multiple of the line size.

In fragmented mode, the maximum resolution line supported on the DisplayPort subsystem is 20 KB. Under a Linux system, the smallest resolution of memory available is 4 KB (MMU resolution). This mode is only used if the line size is more than 4 KB. Software can divide a single line into multiple fragments to store the single line data payload in a non-contiguous space.

In fragmented mode, each descriptor is divided in up to five fragments. Each fragment can store up to 4 KB of data. Software can divide line payload (20 KB) in five sub-payloads. Because it is possible to start and end a data payload on a non-4 KB boundary, software can use up to five fragments to store a whole line, and the DPDMA determines an end of fragment and an end of line.

°The fragment descriptor transfer size must be the same as the line size.

-The fragmented descriptor only holds one lines worth of data.

-This is used if a line size is more than 4k and software cannot allocate a contiguous space.

°All fragmented addresses must be 256-byte aligned.

The example in Table: Fragmented Descriptor Example uses a line size of 10 KB with the largest set of contiguous memory available set at 4 KB. The start of the line data pay load is not 4K aligned, (start address is x0000_FF00) The source address for each fragment must be 256-byte aligned. It is acceptable to use less than five fragments, the DPDMA knows this from the line size (horizontal resolution) information provided in the descriptor.

Table 33-11:      Fragmented Descriptor Example

Fragment Address

Actual Address

Size

SRC_ADDR

0000_AF00

256-bytes

SRC_ADDR2

0000_C000

4096

SRC_ADDR3

0000_D000

4096

SRC_ADDR4

0000_F000

1552

SRC_ADDR5

N/A