Manual Tuning

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English
Table 26-31:      Manual Tuning

Task

Register

Register Field

Register Offset

Bits

Value

Disable clock.

reg_clockcontrol

clkctrl_sdclkena

0x2C

2

Clear bit 2

Gate the glitches in the line.

SD_ITAPDLY

SD{0,1}_ITAPCHGWIN

0x314

9 and 25

Set bit 9 and 25

Enable Rx tap delay clock.

SD_ITAPDLY

SD{0,1}_ITAPDLYENA

0x314

8 and 24

Set bit 8 and 24

Select number of taps for DLL.

SD_ITAPDLY

SD{0,1}_ITAPDLYSEL

0x314

7:0 and 23:16

Desired value based on
the clock

Unset the ITAPCHGWIN.

SD_ITAPDLY

SD{0,1}_ITAPCHGWIN

0x314

9 and 25

Clear bit 9
and 25

Set the taps for the desired clock value.

SD_OTAPDLYSEL

SD{0,1}_OTAPDLYSEL

0x318

5:0 and 21:16

Desired value based on
the clock.

Wait for few cycles for the taps to get synchronized.

Set the DLL reset value.

SD_DLL_CTRL

SD{0,1}_DLL_RST

0x358

2 and 18

Set bit 2
and 18

Wait for few cycles

Release DLL from reset.

SD_DLL_CTRL

SD{0,1}_DLL_RST

0x358

2 and 18

Clear bit 2
and 18

Wait until internal

clock to stabilize.

reg_clockcontrol

sdhcclkgen_intclkstable_dsync

0x2C

1

Read

Enable SD clock.

reg_clockcontrol

clkctrl_sdclkena

0x2C

2

Set bit 2