Master 3-state Enables

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

As shown in This Figure, each pin has a master 3-state enable that overrides any interface specific output enable provided by the peripherals. The master enable is logically combined with the interface specific output enable signals (if provided) currently selected by the output enable multiplexer tree to produce a single output enable for connection to the I/O cell.

Access to the master enable control registers is on a bit-by-bit basis as the pins are configured or in parallel by accessing two 32-bit registers.