Master Mode

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

In master mode, the SPI I/O interface can transmit data to a slave or initiate a transfer to receive data from a slave. In this mode, the controller drives the serial clock and slave selects with an option to support the SPI's multi-master mode. The serial clock is derived from the PS clock subsystem.

The controller selects one slave device at a time using one of the three slave select lines. If more than three slave devices need to be connected to the master, it is possible to add a 3-to-8 decoder on the MIO or EMIO interface. The multiplexer is enabled using the spi.Config [PERI_SEL] bit.

The controller initiates messages using up to three individual slave select output signals that can be externally expanded. The controller reads and writes to the slave devices by writing bytes to the 32-bit read/write data port register.