1.Set the direction of the transfer as read and clear the FIFOs. Write 41h to the Control register.
2.Clear the interrupts. Read and write back the read value to the Interrupt_Status register.
3.Enable the timeout, NACK, RX overflow, arbitration lost, DATA, and completion interrupts. Write 22Fh to the I2C.IER register.
4.Write the read data count to the transfer size register and hold bus, if required. Write the read data count value to the Transfer_Size register. If the read data count is greater than the FIFO depth, set the Control [HOLD] register bit.
5.Write the slave address. Write the address to the Address register.
6.Wait for data to be received into the FIFO.
a.If the read data count is greater than the FIFO depth, wait for ISR [DATA] bit = 1. Read 14 bytes from the FIFO. Decrement the read data count by 14 and if it is less than or equal to the FIFO depth, clear the Control [HOLD] register bit.
b.Otherwise, wait for ISR [COMP] bit = 1 and read the data from the FIFO based on the read data count.
7.Check for the completion of the transfer. Check if the read count reaches zero. Otherwise, repeat from step 6.