Memory Protection Unit

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The memory protection unit (MPU) works with the L1 memory system to control the accesses to and from L1 cache and external memory. For a detailed description of the MPU, refer to the Cortex-R5F Technical Reference Manual [Ref 47].

The MPU enables you to partition memory into regions and set individual protection attributes for each region. When the MPU is disabled, no access permission checks are performed, and memory attributes are assigned according to the default memory map. The MPU has a maximum of 16 regions.

Using the MPU memory region programming registers you can specify the following for each region.

Region base address

Region size

Sub-region enables

Region attributes

Region access permissions

Region enable