Mode Register Accesses

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The basic sequence is as follows:

1.Poll MRSTAT.mr_wr_busy until it is 0. This checks that there is no outstanding MR transaction. No writes should be performed to MRCTRL0 and MRCTRL1 if MRSTAT.mr_wr_busy = 1.

2.Write MRCTRL0.mr_type = 1 (for read), and MRCTRL0.mr_rank = 0x1 or 0x2 (depending on which rank you want to read).

3.Write MRCTRL1[15:8] to the address of the mode register to be read.

4.In a separate APB transaction, write MRCTRL0.mr_wr to 1. This bit is self-clearing, and triggers the MR transaction. The DDRC then asserts the MRSTAT.mr_wr_busy while it performs the MR transaction to SDRAM, and no further accesses can be initiated until it is deasserted.

5.Read MRCTRL0.mr_wr to make sure it has been cleared back to 0.

6.Read MRSTAT.mr_wr_busy to make sure the MRR has completed.

7.Read DDR_QOS_CTRL.DDRC_MRR_STATUS to look for bit 0 = 1 and bits 3:1 greater than 0.

8.Read DDR_QOS_CTRL.DDRC_MRR_DATA0 to see the results of the MRR.

9.Read DDR_QOS_CTRL.DDRC_MRR_DATA11 to reset the MRR read FIFO RD pointer.

10.Repeat to read other registers.

For example, the sequence to read MR8 is:

configparams force-mem-accesses 1

 

#Check DDRC.MRSTAT.mr_wr_busy == 0

mrd 0xfd070018

 

#Write DDRC.MRCTRL0.mr_rank and mr_type to indicate read from rank 0.

mwr 0xfd070010 0x11

 

#Write DDRC.MRCTRL1[15:8] to the MR address to be read, in this case 8.

mwr 0xfd070014 0x800

 

#Write DDRC.MRCTRL0.mr_rank and mr_type to indicate read from rank 0, this time setting

#bit 31 = 1 to initiate the MRR.

mwr 0xfd070010 0x80000011

 

#Read DDRC.MRCTRL0 to look for bit 31 to have been cleared

mrd 0xfd070010

 

#Check DDRC.MRSTAT.mr_wr_busy == 0

mrd 0xfd070018

 

#Check DDR_QOS_CTRL.DDRC_MRR_STATUS to look for 0x3 or higher

mrd 0xfd090518

 

#Read DDR_QOS_CTRL.DDRC_MRR_DATA0 to see the results of the MRR

mrd 0xfd09051c

 

#Read DDR_QOS_CTRL.DDRC_MRR_DATA11 to reset the MRR read FIFO RD pointer.

mrd 0xfd090548