Mode Transitions

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The supported mode transitions are shown in This Figure. The transitions are primarily controlled by the resets, the [CEN] bit, the MSR register settings, and a hardware wake-up mechanism.

To enter normal mode from configuration mode the following steps must occur.

Clear can.MSR[LBACK, SNOOP, SLEEP] = 0.

Set can.SRR[CEN] = 1.

To enter sleep mode from normal mode (interrupt generated), set can.MSR[SLEEP] = 1.

Events that cause the controller to exit sleep mode (interrupt generated) include the following steps.

RX signal activity (hardware sets can.MSR[SLEEP] = 0).

TXFIFO or TXHPB activity (hardware sets can.MSR[SLEEP] = 0).

Software writes 0 to can.MSR[SLEEP].

Figure 20-3:      CAN Operating Mode Transitions, Mode Settings

X-Ref Target - Figure 20-3

X15373-can-operating-mode.jpg

Table: CAN Controller Modes of Operation defines the CAN controller modes of operation and corresponding control and status bits.

Table 20-2:      CAN Controller Modes of Operation

[CAN_RESET] bit

Software Reset Register (can.SRR)

Mode Select Register (MSR)
(Read/Write bits)

Status Register (SR)
(Read Only bits)

Operational Mode

SRST
(CAN
Reset)

CEN
(CAN
Enable)

LBACK

SLEEP

SNOOP

CONFIG

LBACK

SLEEP

NORMAL

SNOOP

1

X

X

X

X

X

1

0

0

0

0

Reset

0

1

X

X

X

X

1

0

0

0

0

Reset

0

0

0

X

X

X

1

0

0

0

0

Configuration

0

0

1

1

X

X

0

1

0

0

0

Loop back

0

0

1

0

1

0

0

0

1

0

0

Sleep

0

0

1

0

0

1

0

0

0

1

1

Snoop

0

0

1

0

0

0

0

0

0

1

0

Normal