Modem Control

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The modem control module facilitates the control of communication between a modem and the UART. It contains the Modem Status register, the Modem Control register, the DMSI bit in interrupt status register, and FLOWDEL in the channel status register. This event is triggered whenever the CTS, DSR, RIX, or DCD in the modem status register are being set.

The read-only Modem Status register is used to read the values of the clear to send (CTS), data carrier detect (DCD), data set ready, (DSR) and ring indicator (RI) modem inputs. It also reports changes in any of these inputs and indicates whether automatic flow control mode is currently enabled. The bits in the Modem Status register are cleared by writing a 1 to the particular bit.

The read/write only Modem Control register is used to set the data terminal ready (DTR) and request to send (RTS) outputs, and to enable the Automatic Flow Control Mode register.

By default, the automatic flow control mode is disabled, meaning that the modem inputs and outputs work completely under software control. When the automatic flow control mode is enabled by setting the FCM bit in the Modem Control register, the UART transmission and reception status is automatically controlled using the modem handshake inputs and outputs.

In automatic flow control mode the request to send output is asserted and deasserted based on the current fill level of the receiver FIFO, which results in the far-end transmitter pausing transmission and preventing an overflow of the UART receiver FIFO. The FDEL field in the Flow Delay register (Flow_delay) is used to setup a trigger level on the Receiver FIFO which causes the deassertion of the request to send. It remains Low until the FIFO level has dropped to below four less than FDEL.

Additionally in automatic flow control mode, the UART only transmits while the clear to send input is asserted. When the clear to send is deasserted, the UART pauses transmission at the next character boundary.

If flow control is selected as automatic, then Flow Delay register must be programmed in order to have a control on the inflow of data, which is done by deasserting RTS signal. The value corresponds to the RxFIFO level at which RTS signal will be deasserted. It will be reasserted when the RxFIFO level drops to four below the value programmed in the Flow Delay register.

The uart.Channel_sts [FLOWDEL] register bit is used to monitor the RxFIFO level in comparison with the flow delay trigger level. The [FLOWDEL] bit is set whenever the RxFIFO level is greater than or equal to trigger the level programmed in the Flow Delay register.

The trigger level programmed in the Flow Delay register has no dependency on the Rx Trigger Level register. This is to only control the inflow of data using the RTS modem signal.

The CPU will be interrupted by receive data only on receipt of an Rx Trigger interrupt. Data is retrieved based on the trigger level programmed in the Rx Trigger Level register.