Monitoring ECC Status

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

1.Read the ECC error counter register (DDRC.ECCERRCNT) to see the number of correctable and uncorrectable ECC errors detected.

2.If ECCERRCNT is non-zero, read the ECC status register (DDRC.ECCSTAT), which provides the bit number corrected by single-bit ECC error, single-bit error indicators, and double-bit error indicators. See Encoding for Corrected Bit Number for the encoding used for the status register field DDRC.ECCSTAT [corrected_bit_num].

3.Read the DDRC.{ECCCADDR0, ECCCADDR1} register to see the bank/row/column information of the corrected ECC error.

4.Read the DDRC.{ECCUADDR0, ECCUADDR1} register to see the bank/row/column information of the uncorrected ECC error.