Multi-Purpose Register (DDR4 Only)

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

This section describes how MPR reads and MPR writes are performed. The DDR4 SDRAMs contain four 8-bit programmable MPRs that can be used for DQ training, CA parity log, MRS readout, or for vendor specific purposes. The registers can be accessed when the SDRAM is in MPR mode and MRCTRL0.mpr_en is set to 1.

For an MPR write, the SoC core must perform the following steps:

1.Issue MRS command to SDRAM MR3 to put the SDRAM into MPR mode. The register MRCTRL0.mpr_en must be set to 0. The MPR page selection, MR3[1:0] must also be selected at this time.

2.Wait until MRSTAT.mr_wr_busy is 0. Write MRCTRL1.mr_data, where MRCTRL1.mr_data[7:0] = <MPR data>.

3.Write MRCTRL0, where MRCTRL0.mr_addr = MPR Location, MRCTRL0.mr_type = write, MRCTRL0.mr_wr = 1 and MRCTRL0.mpr_en = 1. This causes the DDRC to issue the MPR Write.

4.Issue MRS command to SDRAM MR3 to exit the SDRAM from MPR mode. The register MRCTRL0.mpr_en must be set to 0.

For an MPR Read, the SoC core must perform the following steps:

1.If retry is enabled by CRCPARCTRL1.crc_parity_retry_enable = 1, disable reads and writes from being issued on the DFI by setting DBG1.dis_dq = 1 and polling DBGCAM.wr_data_pipeline_empty and DBGCAM.rd_data_pipeline_empty, to ensure that all outstanding commands have been sent on the DFI. Poll CRCPARSTAT.cmd_in_err_window until it equals 0, to ensure that no parity error has occurred. If software intervention is enabled by CRCPARCTL1.alert_wait_for_sw, also monitor CRCPARSTAT.dfi_alert_err_int and CRCPARSTAT.dfi_alert_err_fatl_int during the polling CRCPARSTAT.cmd_in_err_window. If one or more of them are asserted before the polling is done, retry procedure must be completed prior to the subsequent steps.

Note:   If software performs MPR read during software intervention time of retry to read parity/CRC error log from SDRAM, do not poll CRCPARSTAT.cmd_in_err_window.

2.Issue MRS command to SDRAM MR3 to put the SDRAM into MPR mode. The register MRCTRL0.mpr_en must be set to 0. The MPR page selection, MR3[1:0] and read format, MR3[12:11] must also be selected at this time. A typical sequence is:

#Read value in DDRC.INIT4.emr3
set curval "0x[string range [mrd -force 0xfd0700E0] end-8 end]"
set current_emr3 [expr {$curval & 0x0000FFFF}]

#Clear bits 0, 1, 2, 11, and 12
set wrval [expr {$current_emr3 & 0x0000E7F8}]

#Set MPR page [1:0], MPR mode [2], and Read Format [12:11]
#Read Format: 00=serial, 01=parallel, 10=staggered
#Page 0 is parallel, others must be serial
set page 0x2
set mpr_mode [expr {1 << 2}]
set read_format [expr {00 << 11}]
set wrval [expr {$wrval + $page + $mpr_mode + $read_format}]

#Set MRCTRL0 bits to write to rank0 of MR3
mwr 0xFD070010 0x00003010

#Set MRCTRL1 to write data
mwr 0xFD070014 $wrval

#Set MRCTRL0 bit 31 to trigger the write to MR3
mwr 0xFD070010 0x80003010

3.Wait until MRSTAT.mr_wr_busy is 0. Write MRCTRL1.mr_data, where MRCTRL1.mr_data[1:0] = 00.

#Read MRSTAT.mr_wr_busy
mrd 0xFD070018

#Set MRCTRL1.mr_data = 0
mwr 0xFD070014 0x00000000

4.Write MRCTRL0, where MRCTRL0.mr_addr = MPR Location, MRCTRL0.mr_type = read, MRCTRL0.mr_wr = 1, and MRCTRL0.mpr_en = 1. This causes the DDRC to issue the MPR Read.

#Set MPR location [15:12], MR type [0] = 1 (read), MR rank [4], and MPR Enable [1] = 1 (MPR)
set mpr_location [expr {0x3 << 12}]
set mr_type 1
set mr_rank [expr {1 << 4}]
set mpr_enable [expr {0 << 1}]
set mrctrl0_val [expr {$mpr_location + $mr_type + $mr_rank + $mpr_enable}]

#Set MRCTRL0
mwr 0xFD070010 $mrctrl0_val

#Set MRCTRL0 bit 31 to trigger the write to MR3
set mr_wr [expr {1 << 31}]
set mrctrl0_val [expr {$mrctrl0_va
l + $mr_wr}]
mwr 0xFD070010 $mrctrl0_val

The mode register contents are available on DDR_QOS_CTRL.DDRC_MRR_DATA[11:0], qualified by DDR_QOS_CTRL.DDRC_MRR_STATUS.VALID.

DDR_QOS_CTRL.DDRC_MRR_STATUS[0] == 1 indicates that valid data is available in the read FIFO.

DDR_QOS_CTRL.DDRC_MRR_STATUS[3:1] indicates how many valid data entries are available in the FIFO.

Each FIFO entry is 288 bits, representing a burst of four 72-bit values.

DDRC_MRR_DATA0 = UI0 of bytes 3:0

DDRC_MRR_DATA1 = UI0 of bytes 7:4

DDRC_MRR_DATA2 = UI0 of the ECC byte

This is the MSB for serial mode reads.

This pattern repeats four times:

DDRC_MRR_DATA3 = UI1 of bytes 3:0

up to:

DDRC_MRR_DATA11 = UI3 of the ECC byte

Reading DDRC_MRR_DATA11 pops the FIFO and makes the next 288 bits available in DDRC_MRR_DATA[11:0].

When all the data has been read from the FIFO, it is safe to move to the next step.

5.Issue MRS command to SDRAM MR3 to exit the SDRAM from MPR mode. The register MRCTRL0.mpr_en must be set to 0.

6.If reads/writes have been disabled in step 1, re-enable reads and writes on the DFI by setting DBG1.dis_dq = 0.