Multi-master Mode

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

For multi-master mode, the controller is programmed for master mode [MODE_SEL] and can initiate transfers on any of the slave selects. When the software is ready to initiate a transfer, it enables the controller using the [SPI_EN] bit. When the transaction is done, the software disables the controller. The controller cannot be selected by an external master when the controller is in master mode.

The controller detects another master on the bus by monitoring the open-drain slave select signal (active Low). The detection mechanism is enabled by the [Modefail_gen_en]. When the controller detects another master, it sets the spi.ISR [MODE_FAIL] interrupt status bit and clears the spi.Enable [SPI_EN] control bit. The software can receive the [MODE_FAIL] interrupt so it can abort the transfer, reset the controller, and re-send the transfer.